A typical computer system includes a number of peripheral devices (hereinafter often referred to as "peripherals" or "devices") that provide mass storage for the system and allow communication outside the system. These peripherals include disk drives, tape drives, terminals, and the like. However, the peripherals normally operate on a time scale that is at least an order of magnitude slower than the operation of other functional units within the system. While it is a known practice to interface peripheral controllers directly to a main system bus, this usually requires a large amount of overhead associated with each peripheral controller. Accordingly, it is a known practice to couple the peripheral controllers to a peripheral sub-bus, and to provide an intelligent I/O channel processor (hereinafter "IOCP") for controlling communication between the sub-bus and the main system bus. The sub-bus differs from the system bus in that it is significantly longer and operates at a lower speed. To simplify terminology, the peripheral sub-bus will often be referred to simply as the "bus." Directions on the bus will be designated relative to the IOCP, with terms such as "transmit" and "outbound" referring to communications from the IOCP, and terms such as "receive" and "inbound" referring to communications to the IOCP.
Any bus system requires that the data be timed with respect to some clock signal for validation. In the case of a bi-directional bus, such validation is needed in both directions. Prior art buses have generally been sufficiently short or sufficiently slow that the signal propagation time between devices on the bus has not proved problematical. In such cases, a single clock line from the IOCP to the devices in sequential party line fashion has sufficed. A receiving device latches the bus data in at a predetermined time in the clock cycle; a sending device places its data on the bus at another predetermined time in the clock cycle.
However, attempts to operate with faster and/or longer buses have necessitated a variety of asynchronous approaches, since the time at which the data comes back to the IOCP becomes increasingly indeterminate with respect to the clock signal at the IOCP. One prior art asynchronous approach has the IOCP remove its own data or instruction from the bus and then merely wait for the state of the bus lines to change. The change in bus state then signifies that the expected response is available. However, the IOCP must either sample the bus to make sure that the data has stabilized, or alternately, delay reading the bus for some predetermined time interval.
An alternate prior art asynchronous approach uses an outbound clock generated by the IOCP and an inbound clock generated by the device sending information back to the IOCP. However, since the two clocks are not synchronized with respect to one another, there may still occur situations where the relevant inbound clock transition occurs at a time when the IOCP is undergoing some internal transition in synchronization with its own (outbound) clock.